module rx_top_test(SW, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7, LEDR, LEDG, GPIO_1, CLOCK_50);

input [17:0] SW; //slide switches
input [3:0] KEY; //pushbuttons
input CLOCK_50;
input [35:0] GPIO_1;
output [6:0] HEX0; //hex display
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output [6:0] HEX4;
output [6:0] HEX5;
output [6:0] HEX6;
output [6:0] HEX7;
output [17:0] LEDR; //red LEDs
output [7:0] LEDG; //green LEDs

wire reset = SW[0];
// MII signals - just assign these to appropriate GPIO instead
wire [3:0] rxd;
wire rx_dv = GPIO_1[7];
wire rx_er = GPIO_1[9];
wire rx_clk = GPIO_1[8];
// switch fabric interface
wire rxd_fifo_rdreq = SW[2];
wire rxd_fifo_empty;
wire [7:0] rxd_fifo_q;
wire length_fifo_rdreq = SW[1];
wire length_fifo_empty;
wire [11:0] length_fifo_q;
// debug signals
wire [1:0] state_out;
wire [31:0] hex_dat = {2'b0, state_out, rxd[3:0], rxd_fifo_q[7:0], 3'b0, length_fifo_q[11], 1'b0, length_fifo_q[10:0]};

assign rxd[3] = GPIO_1[3];
assign rxd[2] = GPIO_1[4];
assign rxd[1] = GPIO_1[5];
assign rxd[0] = GPIO_1[6];

assign LEDG[0] = length_fifo_empty;
assign LEDG[4:1] = 4'b0;
assign LEDG[7:5] = {reset, clk, rx_clk};
assign LEDR[0] = rxd_fifo_empty;
assign LEDR[17:1] = 0; 

reg clk_key;
wire clk = (SW[3])?clk_key:CLOCK_50;

//hex6 rxd
//hex[5:4] rxd_fifo_q
//hex[2:0] length_fifo_q;

// clk will come from CLOCK_50, rx_clk will come from GPIO
always @(negedge KEY[0]) clk_key <= ~clk_key;

rx_top rx_top_inst
(
	.clk(clk) ,	// input  clk_sig
	.reset(reset) ,	// input  reset_sig
	.rx_clk(rx_clk) ,	// input  rx_clk_sig
	.rxd(rxd) ,	// input [3:0] rxd_sig
	.rx_dv(rx_dv) ,	// input  rx_dv_sig
	.rx_er(rx_er) ,	// input  rx_er_sig
	.rxd_fifo_rdreq(rxd_fifo_rdreq) ,	// input  rxd_fifo_rdreq_sig
	.rxd_fifo_empty(rxd_fifo_empty) ,	// output  rxd_fifo_empty_sig
	.rxd_fifo_q(rxd_fifo_q) ,	// output [7:0] rxd_fifo_q_sig
	.length_fifo_rdreq(length_fifo_rdreq) ,	// input  length_fifo_rdreq_sig
	.length_fifo_empty(length_fifo_empty) ,	// output  length_fifo_empty_sig
	.length_fifo_q(length_fifo_q), 	// output [11:0] length_fifo_q_sig
	.state_out(state_out)
);

segment_hex_decoder dec7(.v(hex_dat[31:28]), .segments(HEX7));
segment_hex_decoder dec6(.v(hex_dat[27:24]), .segments(HEX6));
segment_hex_decoder dec5(.v(hex_dat[23:20]), .segments(HEX5));
segment_hex_decoder dec4(.v(hex_dat[19:16]), .segments(HEX4));
segment_hex_decoder dec3(.v(hex_dat[15:12]), .segments(HEX3));
segment_hex_decoder dec2(.v(hex_dat[11:8]),  .segments(HEX2));
segment_hex_decoder dec1(.v(hex_dat[7:4]),   .segments(HEX1));
segment_hex_decoder dec0(.v(hex_dat[3:0]),   .segments(HEX0));

endmodule

// this module borrowed from code written by Albert Meixner for another project
module segment_hex_decoder(v, segments);
	input [3:0] v;
	output[6:0]     segments;

	reg [6:0]       seg;
	
	assign segments = ~seg;
	
	always @(v)
	case ( v )
		4'h0:   seg <= 7'b0111111;
		4'h1:   seg <= 7'b0000110;
		4'h2:   seg <= 7'b1011011;
		4'h3:   seg <= 7'b1001111;
		4'h4:   seg <= 7'b1100110;
		4'h5:   seg <= 7'b1101101;
		4'h6:   seg <= 7'b1111101;
		4'h7:   seg <= 7'b0000111;
		4'h8:   seg <= 7'b1111111;
		4'h9:   seg <= 7'b1101111;
		4'ha:   seg <= 7'b1110111;
		4'hb:   seg <= 7'b1111100;
		4'hc:   seg <= 7'b0111001;
		4'hd:   seg <= 7'b1011110;
		4'he:   seg <= 7'b1111001;
		4'hf:   seg <= 7'b1110001;
	endcase

endmodule
